1. Field of the Invention
The invention generally relates to a semiconductor memory device. More particularly, the invention relates to a refresh operation of a DRAM (Dynamic Random Access Memory).
2. Background Art
In order to implement SOC (System On Chip) at low cost, higher integration has been required especially for an embedded DRAM in recent years. It is a memory array portion having a plurality of memory cells which occupies most of the memory area. In order to implement higher integration, the memory cell area has been reduced by miniaturization technology of memory cell transistors and memory cell capacitors using a high dielectric constant insulating film.
For example, in the case of stacked memory cells, capacitor capacitance is assured by introducing a new high dielectric constant insulating film in view of reduction in the capacitor surface area caused by miniaturization. In order to increase the capacitor capacitance of the memory cells, however, the insulating film thickness needs to be reduced to the minimum, which increases a tunneling leakage current of the capacitor insulating film. Moreover, since logic compatibility is strongly required in the miniaturization process, silicidated storage nodes are used, which increases junction leakage of the storage nodes. Therefore, the charge retention time of the memory cells is reduced and word lines need to be activated more often for a refresh operation as compared to conventional examples.
Conventionally, the refresh frequency has been increased by increasing the input frequency of an external refresh command (such as an auto refresh command) to a DRAM. In this case, however, the access efficiency of external read/write access to the DRAM is effectively reduced and the system performance is limited. For example, in the case of refreshing a DRAM having a charge retention time of 1 millisecond (ms) and 4096 word lines, an external auto refresh command needs to be applied every 244 nanoseconds (ns). In the case where the DRAM has a random cycle of 100 ns, a refresh command needs to be applied every two cycles.
There is also a technology of reducing the input frequency of an external refresh command by activating a plurality of word lines in a DRAM in response to an external refresh command. However, activating many memory blocks at the same time increases an instantaneous current, causing reduction in an operation margin due to a power supply voltage drop and noise. Therefore, the maximum number of word lines that can be activated at the same time is limited. Accordingly, when the charge retention time of memory cells is reduced, it is inevitable to increase the input frequency of an external refresh command.
In view of the above technologies, Japanese Laid-Open Patent Publication No. 2005-203092 (Patent document 1) describes a technology of simultaneously refreshing a memory block that is not externally read/write accessed (a memory block that is not externally accessed) during a normal read/write access period.
FIG. 26 is a block diagram showing a structure of a main part of a conventional semiconductor memory device described in Patent document 1.
In FIG. 26, RAC indicates a row address counter; banks 0, 1, . . . , 14, and 15 indicate a memory bank; WADD<6:0> indicates a word line address; WRAC<6:0> indicates a refresh word line address; BSEL<15:0> indicates a bank select signal; and RBSEL<15:0> indicates a refresh bank select signal.
In this structure, a memory bank that is different from the one designated by the bank select signal BSEL<15:0> is selected by the refresh bank select signal RBSEL<15:0>, whereby refresh can be conducted simultaneously with external access. In the case where an externally accessed memory bank conflicts with a memory bank to be refreshed, the memory bank cannot be refreshed. Such a bank conflict is avoided by a system (not shown) having the semiconductor memory device.
Of the word lines in each memory bank, word lines that have already been refreshed are independently stored in the row address counters RAC respectively corresponding to the memory banks. Since the row address counters RAC thus manage the addresses of word lines to be refreshed in the respective memory banks, the system does not need to consider the management of addresses of word lines in each memory bank.
Accordingly, in the technology described in Patent document 1, all the memory cells in the plurality of memory banks in the semiconductor memory device can be refreshed by merely applying the refresh bank select signal RBSEL<15:0> to each memory bank while avoiding a predetermined number of bank conflicts. For example, in the case where each memory bank includes 128 word lines, refresh of all the memory cells is assured by avoiding bank conflicts by the system so that 128 refresh commands are applied to each memory bank within the charge retention time of the memory cells.
However, in a semiconductor memory device that does not have a memory bank structure, a system having the semiconductor memory device cannot access memory blocks in the semiconductor memory device on a block-by-block basis. Therefore, it is impossible for the system to arbitrate a conflict between access to an external access memory block (an externally accessed memory block) and access to an internal refresh memory block (a memory block to be internally refreshed) by the technology described in Patent document 1.
In the technology of Patent document 1, the row address counters respectively corresponding to the memory banks are dispersedly located within the semiconductor memory device, resulting in increase in the area of the semiconductor memory device.
Moreover, in the case where the system conducts refresh management while considering only the bank conflicts, the system does not recognize refresh information of the word lines in each memory bank. Therefore, the refresh bank select signal RBSEL<15:0> is continuously applied to the semiconductor memory device. As a result, refresh is conducted more than a required number of times within the charge retention time of the memory cells, resulting in increase in current consumption. In order to avoid this problem, complicated refresh management by the system or internal control of the DRAM are necessary to stop the refresh operation. However, Patent document 1 does not disclose such management and control.